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A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs.

, , and . FPL, page 451-452. IEEE Computer Society, (2018)

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A partitioned instruction queue to reduce instruction wakeup energy., , , , and . IJHPCN, 1 (4): 153-161 (2004)The Velox Transactional Memory Stack., , , , , , , , , and 14 other author(s). IEEE Micro, 30 (5): 76-87 (2010)EVX: Vector execution on low power EDGE cores., , , , , , and . DATE, page 1-4. European Design and Automation Association, (2014)unreadTVar: Extending Haskell Software Transactional Memory for Performance., , , , , and . Trends in Functional Programming, volume 8 of Trends in Functional Programming, page 89-104. Intellect, (2007)Implications of non-volatile memory as primary storage for database management systems., , , , and . SAMOS, page 164-171. IEEE, (2016)On the selection of adder unit in energy efficient vector processing., , , , , and . ISQED, page 143-150. IEEE, (2013)Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm., , , , , and . PDP, page 184-191. IEEE Computer Society, (2016)A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems., , , , , , and . CARLA, volume 796 of Communications in Computer and Information Science, page 3-20. Springer, (2017)AMMC: Advanced Multi-Core Memory Controller., , , , , , and . FPT, page 292-295. IEEE, (2014)VALib and SimpleVector: tools for rapid initial research on vector architectures., , , , , and . Conf. Computing Frontiers, page 7:1-7:10. ACM, (2014)