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A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs., , , and . IEEE Trans. on Circuits and Systems, 58-II (11): 748-752 (2011)Exploiting Weak PUFs From Data Converter Nonlinearity - E.g., A Multibit CT ΔΣ Modulator., , and . IEEE Trans. on Circuits and Systems, 63-I (7): 994-1004 (2016)A 1 V, 12-bit wideband continuous-time /spl Sigma//spl Delta/ modulator for UMTS applications., , and . ISCAS (1), page 921-924. IEEE, (2003)Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators., , and . ISCAS (1), page 1037-1040. IEEE, (2003)A Background DAC Error Estimation in Sigma-Delta ADCs using a Pseudo Random Noise based Correlation Technique., and . ISCAS, page 1549-1552. IEEE, (2009)A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs., , , , and . ISCAS, page 2897-2900. IEEE, (2008)Multirate cascaded continuous time Sigma-Delta modulators., , , and . ISCAS (4), page 225-228. IEEE, (2002)Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators., , and . ISCAS (1), page 1076-1079. IEEE, (2004)A clock jitter insensitive multibit DAC architecture for high-performance low-power continuous-time ΣΔ modulators., , , , and . ICECS, page 958-961. IEEE, (2003)A front-end circuit with active spike and LFP separation via a switched capacitor filter structure for neural recording applications., and . ISCAS, page 2231-2234. IEEE, (2012)