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From RTL IP to functional system-level models with extra-functional properties.

, , , , and . CODES+ISSS, page 547-556. ACM, (2012)

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Mapping of Concurrent Object-Oriented Models to Extended Real-Time Task Networks., , , and . FDL, page 43-48. ECSI, Electronic Chips & Systems design Initiative, (2010)Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems., , , and . FDL, page 56-61. ECSI, Electronic Chips & Systems design Initiative, (2010)Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking., , , and . DATE, page 1167-1172. EDA Consortium San Jose, CA, USA / ACM DL, (2013)CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties., , , , , , , , , and 16 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, (2017)Towards power management verification of time-triggered systems using virtual platforms., , , , and . SAMOS, page 81-88. ACM, (2018)SAFEPOWER Project: Architecture for Safe and Power-Efficient Mixed-Criticality Systems., , , , , , , , , and 3 other author(s). DSD, page 294-300. IEEE Computer Society, (2016)An ESL timing & power estimation and simulation framework for heterogeneous socs., , , , , , , , , and . ICSAMOS, page 181-190. IEEE, (2014)PolyDyn - Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs., , , , , and . Dynamically Reconfigurable Systems, Springer, (2010)Towards Distributed Runtime Monitoring with C++ Contracts., , and . COINS, page 141-145. ACM, (2019)OSSS-Channels: Modelling and Synthesis of Communication., , , , and . FDL, page 327-335. ECSI, (2006)