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Towards power management verification of time-triggered systems using virtual platforms.

, , , , and . SAMOS, page 81-88. ACM, (2018)

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Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (10): 1586-1599 (2015)SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems., , , , , , , , , and 8 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, (2017)Towards power management verification of time-triggered systems using virtual platforms., , , , and . SAMOS, page 81-88. ACM, (2018)Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Functional Test Environment for Time-Triggered Control Systems in Complex MPSoCs Using GALI., , , , and . DSD, page 711-718. IEEE Computer Society, (2018)Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames., , , and . IEEE Trans. VLSI Syst., 24 (3): 932-943 (2016)Modeling symmetrical independent gate FinFET using predictive technology model., , , , and . ACM Great Lakes Symposium on VLSI, page 299-304. ACM, (2013)Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes., , , and . DAC, page 212:1-212:6. ACM, (2014)Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach., , , and . ASP-DAC, page 743-748. IEEE, (2015)