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Exploiting UML based validation for compliance checking of TLM 2 based models., , and . Design Autom. for Emb. Sys., 16 (2): 93-113 (2012)Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing., , and . Design Autom. for Emb. Sys., 8 (4): 309-326 (2003)High performance 3D-FFT implementation., , , and . ISCAS, page 2227-2230. IEEE, (2013)Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library., , , and . VLSI Design, page 400-405. IEEE Computer Society, (1998)Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors., , and . VLSI Design, page 261-266. IEEE Computer Society, (2008)Optimal Clock Period for Synthesized Data Paths., , and . VLSI Design, page 134-139. IEEE Computer Society, (1997)Specification of Exception Handling in Grammar-Based Hardware Synthesis., , and . EUROMICRO, page 10038-10041. IEEE Computer Society, (1998)Impact of crosstalk and process variation on capture power reduction for at-speed test., , and . VTS, page 1-6. IEEE Computer Society, (2016)Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures., , , and . DATE, page 730-735. IEEE Computer Society, (2005)Performance-Energy Trade-off in CMPs with Per-Core DVFS., , and . ARCS, volume 10793 of Lecture Notes in Computer Science, page 225-238. Springer, (2018)