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Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing.

, , and . Design Autom. for Emb. Sys., 8 (4): 309-326 (2003)

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Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing., , and . Design Autom. for Emb. Sys., 8 (4): 309-326 (2003)Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards., , and . FPL, volume 1896 of Lecture Notes in Computer Science, page 201-210. Springer, (2000)Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing., , and . IEEE International Workshop on Rapid System Prototyping, page 66-. IEEE Computer Society, (2002)Evaluation of Various Routing Architectures for Multi-FPGA Boards., , and . VLSI Design, page 262-267. IEEE Computer Society, (2000)Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards., , and . FPT, page 298-301. IEEE, (2002)