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Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design

, and . ACM Transactions on Embedded Computing Systems, 18 (5): 43 (2019)
DOI: 10.1145/3356583

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Automated Sensor Firmware Development : Generation, Optimization, and Analysis, , , , , and . MBMV 2019 : 22nd Workshop : Methods and Description Languages for Modelling and Verification of Circuits and Systems, VDE Verlag, (2019)Power-mode-aware Memory Subsystem Optimization for Low-power System-on-Chip Design, and . ACM Transactions on Embedded Computing Systems, 18 (5): 43 (2019)Low Power Memory Allocation and Mapping for Area-Constrained Systems-on-Chips, , and . EURASIP Journal on Embedded Systems, (2016)Low power memory allocation and mapping for area-constrained systems-on-chips., , and . EURASIP J. Emb. Sys., (2017)Combined MPSoC Task Mapping and Memory Optimization for Low-Power, , , and . 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), page 121-124. Piscataway, IEEE, (2019)Hybrid instruction set simulation for fast and accurate memory access profiling, and . 2017 13th Workshop on Intelligent Solutions in Embedded Systems (WISES), page 23-28. Piscataway, IEEE, (2017)A Backend Tool for the Integration of Memory Optimizations into Embedded Software, and . 2019 Forum for Specification and Design Languages (FDL), Piscataway, IEEE, (2019)Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded Systems, and . 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), page 347-353. Piscataway, IEEE, (2019)Entwurf und Implementierung einer Prozessinterkommunikation für Multi-Core CPUs.. Echtzeit, page 59-68. Springer, (2013)Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures, , and . 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), page 763-770. Piscataway, IEEE, (2016)