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Disambiguation of "Yan, Guihai"

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SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks.

, , , , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (1): 8:1-8:27 (2019)

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Shuhao Yan University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Guangpu Yang University of Stuttgart

Xiliu Yang University of Stuttgart

Univ. -Prof. Dr. -Ing. Bin Yang University of Stuttgart

 

Other publications of authors with the same name

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling., , , , and . Journal of Systems Architecture - Embedded Systems Design, 56 (10): 534-542 (2010)Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications., , , and . DATE, page 208-213. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores., , , and . ASP-DAC, page 394-399. IEEE, (2014)Tetris: re-architecting convolutional neural network computation for machine learning accelerators., , , , and . ICCAD, page 21. ACM, (2018)SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators., , , , , , and . DATE, page 343-348. IEEE, (2018)M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay., , , , , and . Asian Test Symposium, page 437-442. IEEE Computer Society, (2009)BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission., , , and . IEICE Transactions, 91-C (10): 1690-1697 (2008)Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications., , , and . IEEE Trans. VLSI Syst., 22 (12): 2476-2487 (2014)A unified online Fault Detection scheme via checking of Stability Violation., , and . DATE, page 496-501. IEEE, (2009)ACR: Enabling computation reuse for approximate computing., , , and . ASP-DAC, page 643-648. IEEE, (2016)