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Disambiguation of "Han, Yinhe"

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Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores.

, , , and . ASP-DAC, page 394-399. IEEE, (2014)

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Liao Han University of Stuttgart

Qi Han

Udo-Ernst Haner University of Stuttgart

Dr. phil. Vanessa Hanke University of Stuttgart

Dr. Yuliya Hanesch University of Stuttgart

 

Other publications of authors with the same name

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design., , , and . J. Comput. Sci. Technol., 28 (1): 119-128 (2013)A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications., , , and . J. Comput. Sci. Technol., 29 (2): 239-246 (2014)Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling., , , , and . Journal of Systems Architecture - Embedded Systems Design, 56 (10): 534-542 (2010)Fast Packet Classification using Group Bit Vector., , , and . GLOBECOM, IEEE, (2006)On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island., , , and . VLSI-DAT, page 1-4. IEEE, (2015)On predicting NBTI-induced circuit aging by isolating leakage change., , , , and . ISQED, page 46-52. IEEE, (2013)A New Post-Silicon Debug Approach Based on Suspect Window., , and . VTS, page 85-90. IEEE Computer Society, (2009)Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs., , , and . DATE, page 933-936. IEEE, (2010)Rapid and Energy-Efficient Testing for Embedded Cores., , , , and . Asian Test Symposium, page 8-13. IEEE Computer Society, (2004)Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC., , , , and . Asian Test Symposium, page 181-186. IEEE Computer Society, (2011)