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Disambiguation of "Liu, Leibo"

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Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations

, , , , , and . IEEE transactions on circuits and systems. 1, Regular papers, 69 (11): 4558-4571 (2022)
DOI: 10.1109/TCSI.2022.3193928

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Univ. -Prof. Dr. Na Liu University of Stuttgart

Synthesized complex-frequency excitation for ultrasensitive molecular sensing, , , , , , , , , and . eLight, 4 (1): 1 (2024)

Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Yanchao Liu University of Stuttgart

 

Other publications of authors with the same name

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time., , , , , , and . IEEE Trans. VLSI Syst., 22 (5): 983-994 (2014)Low-Power Reconfigurable Processor Utilizing Variable Dual VDD., , , and . IEEE Trans. on Circuits and Systems, 60-II (4): 217-221 (2013)A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency., , , , and . IEEE Trans. on Circuits and Systems, 62-II (1): 75-79 (2015)A fast and robust traffic sign recognition method using ring of RIBP histograms based feature., , , and . ROBIO, page 2570-2575. IEEE, (2014)Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor., , , , , , , , and . ISCAS, page 897-900. IEEE, (2013)A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing., and . ISCAS, page 1182-1185. IEEE, (2015)A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space., , , and . CICC, page 1-4. IEEE, (2015)Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding., , , , and . EMC/HumanCom, volume 260 of Lecture Notes in Electrical Engineering, page 545-555. Springer, (2013)Mixed-level modeling for network on chip infrastructure in SoC design., , , and . APCCAS, page 911-914. IEEE, (2010)A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing., , , , and . IEEE Trans. VLSI Syst., 24 (4): 1305-1318 (2016)