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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing.

S. Yin, P. Ouyang, T. Chen, L. Liu, and S. Wei. IEEE Trans. VLSI Syst., 24 (4): 1305-1318 (2016)

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Other publications of authors with the same name

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures.S. Yin, D. Liu, Y. Peng, L. Liu, and S. Wei. IEEE Trans. VLSI Syst., 24 (2): 507-520 (2016)An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices.L. Liu, W. Zhu, S. Yin, E. Tang, and P. Peng. IEEE Trans. Consumer Electronics, 60 (1): 137-145 (2014)ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor.L. Liu, W. Jia, S. Yin, D. Wang, G. Sun, E. Tang, and S. Wei. SCIENCE CHINA Information Sciences, 56 (6): 1-16 (2013)MapReduce inspired loop mapping for coarse-grained reconfigurable architecture.S. Yin, S. Shao, L. Liu, and S. Wei. SCIENCE CHINA Information Sciences, 57 (12): 1-14 (2014)An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video.W. Zhang, L. Liu, S. Yin, R. Zhou, S. Cai, and S. Wei. SCIENCE CHINA Information Sciences, 56 (7): 1-14 (2013)An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications.L. Liu, C. Deng, D. Wang, M. Zhu, S. Yin, P. Cao, and S. Wei. CICC, page 1-4. IEEE, (2013)Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms.S. Yin, P. Ouyang, L. Liu, and S. Wei. DATE, page 1-6. European Design and Automation Association, (2014)Battery aware tasks allocating algorithm for multi-battery operated system.P. Ouyang, S. Yin, L. Liu, and S. Wei. APCCAS, page 875-878. IEEE, (2010)A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems.S. Yin, J. Cui, A. Luo, L. Liu, and S. Wei. ASICON, page 224-227. IEEE, (2011)CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache.S. Yin, W. Xu, J. Li, L. Liu, and S. Wei. IEEE Trans. VLSI Syst., 24 (7): 2548-2561 (2016)

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Disambiguation of "Yin, Shouyi"

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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing.

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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing.