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An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

X. Xu, H. Liang, K. Zhou, G. Ma, Z. Huang, M. Yi, T. Ni, and Y. Lu. ATS, page 59-62. IEEE, (2018)

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Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.H. Liang, S. Hellebrand, and H. Wunderlich. J. Electronic Testing, 18 (2): 159-170 (2002)A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding.H. Liang, W. Zhan, Q. Luo, and C. Jiang. PRDC, page 11-16. IEEE Computer Society, (2009)Pulse shrinkage based pre-bond through silicon vias test in 3D IC.C. Hao, and H. Liang. VTS, page 1-6. IEEE Computer Society, (2015)A Region-Based Through-Silicon via Repair Method for Clustered Faults.T. Ni, H. Liang, M. Nie, X. Xu, A. Yan, and Z. Huang. IEICE Transactions, 100-C (12): 1108-1117 (2017)A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs.M. Yi, J. Bian, T. Ni, C. Jiang, H. Chang, and H. Liang. IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (4): 755-766 (2019)A Dictionary-Based Test Data Compression Method Using Tri-State Coding.T. Chen, C. Lin, H. Liang, and F. Ren. ATS, page 42-47. IEEE, (2018)A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE.Z. Huang, Y. Zhang, Z. Su, H. Liang, H. Yao, and T. Ni. ATS, page 121-126. IEEE, (2018)Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs.T. Song, H. Liang, Z. Huang, T. Ni, and Y. Sun. IEICE Electron. Express, 18 (2): 20200420 (2021)Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing.M. Yi, H. Liang, K. Zhan, and C. Jiang. CSE (2), page 698-702. IEEE Computer Society, (2009)Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding.C. Hao, H. Liang, L. Yang, and Y. Ouyang. VLSI-DAT, page 1-4. IEEE, (2014)

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An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

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An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.