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NBTI mitigation by M-IVC with input duty cycle and randomness constraints., , , , , and . EWDTS, page 1-5. IEEE, (2016)Research on physical unclonable functions circuit based on three dimensional integrated circuit., , , , and . IEICE Electronic Express, 15 (23): 20180782 (2018)Temperature-Aware Floorplanning for Fixed-Outline 3D ICs., , , , , , , and . IEEE Access, (2019)Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware, , , , and . ACM transactions on design automation of electronic systems, 29 (1): 1-3 (2024)An enhanced time-to-digital conversion solution for pre-bond TSV dual faults testing., , , , and . IEICE Electronic Express, 16 (3): 20181105 (2019)An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs., , , , , , , and . ATS, page 59-62. IEEE, (2018)A Novel Built-In Self-Repair Scheme for 3D Memory., , , , and . IEEE Access, (2019)A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (4): 755-766 (2019)A novel in-field TSV repair method for latent faults., , , and . IEICE Electronic Express, 15 (23): 20180873 (2018)A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE., , , , , and . ATS, page 121-126. IEEE, (2018)