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Disambiguation of "Nomura, Masahiro"

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Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits.

, , , and . ISSCC, page 436-437. IEEE, (2013)

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Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs., , , , , , , , , and . J. Solid-State Circuits, 46 (4): 806-814 (2011)An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques., , , , , , and . IEICE Transactions, 89-C (3): 334-341 (2006)Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits., , , , , and . CICC, page 1-4. IEEE, (2012)A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates., , , , , , and . DAC, page 984-989. ACM, (2011)A Simple Heuristic for Bayesian Optimization with A Low Budget., and . CoRR, (2019)Optimal Fixed-Budget Best Arm Identification using the Augmented Inverse Probability Weighting Estimator in Two-Armed Gaussian Bandits with Unknown Variances., , , , , and . CoRR, (2022)Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure., and . SSCI, page 1-7. IEEE, (2021)A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations., , , and . J. Solid-State Circuits, 43 (4): 911-918 (2008)Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature., , , , , , , and . IEEE Trans. on Circuits and Systems, 59-II (12): 918-921 (2012)Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits., , , and . J. Solid-State Circuits, 49 (2): 536-544 (2014)