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A scalable, clustered SMT processor for digital signal processing.

, , and . SIGARCH Computer Architecture News, 32 (3): 62-69 (2004)

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Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit., , , and . DFT, page 105-113. IEEE Computer Society, (2000)HIBRID-SOC: a multi-core architecture for image and video applications., , , , , , and . SIGARCH Computer Architecture News, 32 (3): 55-61 (2004)HiBRID-SoC: a multi-core architecture for image and video applications., , , , , , and . ICIP (3), page 101-104. (2003)A Large-Area Integrated Multiprocessor System for Video Applications., , , , and . IEEE Design & Test of Computers, 19 (1): 6-17 (2002)A scalable, clustered SMT processor for digital signal processing., , and . SIGARCH Computer Architecture News, 32 (3): 62-69 (2004)Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams., , , and . SoCC, page 427-431. IEEE, (2009)HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing., , , , , and . VLSI-SOC, page 155-160. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing., , , , , , , , and . VLSI Signal Processing, 41 (1): 9-20 (2005)HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications., , , , , , , , and . DATE, page 20008-20013. IEEE Computer Society, (2003)A multi-core SoC design for advanced image and video compression., , , , , , and . ICASSP (5), page 665-668. IEEE, (2005)