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Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit.

, , , and . DFT, page 105-113. IEEE Computer Society, (2000)

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Guest Editors' Introduction., , and . VLSI Signal Processing, 22 (1): 5-6 (1999)An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor., , , , and . VLSI Signal Processing, 16 (1): 31-40 (1997)The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques., , , , , and . VLSI Signal Processing, 11 (1-2): 51-74 (1995)A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications., , and . VLSI Signal Processing, 41 (2): 139-151 (2005)Architectures for digital signal processing.. Wiley, (1998)Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms., , and . ASAP, page 294-303. IEEE Computer Society, (1997)A multi-core SoC design for advanced image and video compression., , , , , , and . ICASSP (5), page 665-668. IEEE, (2005)A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications., , and . ICASSP (2), page 413-416. IEEE Computer Society, (1994)The Video and Image Processing Emulation System VIPES., , and . International Workshop on Rapid System Prototyping, page 170-175. IEEE Computer Society, (1998)Design Space Exploration of Media Processors: A Parameterized Scheduler., , , and . ICSAMOS, page 41-49. IEEE, (2007)