The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.
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%0 Journal Article
%1 journals/vlsisp/SchonfeldFSPVM95
%A Schönfeld, Mirjam
%A Franzen, Jens
%A Schwiegershausen, Markus
%A Pirsch, Peter
%A Vehlies, Uwe
%A Münzner, Andreas
%D 1995
%J VLSI Signal Processing
%K dblp
%N 1-2
%P 51-74
%T The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.
%U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp11.html#SchonfeldFSPVM95
%V 11
@article{journals/vlsisp/SchonfeldFSPVM95,
added-at = {2008-08-07T00:00:00.000+0200},
author = {Schönfeld, Mirjam and Franzen, Jens and Schwiegershausen, Markus and Pirsch, Peter and Vehlies, Uwe and Münzner, Andreas},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c9cad956809ad0247e69ca067af050cc/dblp},
ee = {http://dx.doi.org/10.1007/BF02106823},
interhash = {d4df5fbaa24da574cfafc97f62f429c6},
intrahash = {c9cad956809ad0247e69ca067af050cc},
journal = {VLSI Signal Processing},
keywords = {dblp},
number = {1-2},
pages = {51-74},
timestamp = {2016-02-02T09:52:55.000+0100},
title = {The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.},
url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp11.html#SchonfeldFSPVM95},
volume = 11,
year = 1995
}
