Author of the publication

HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.

, , , , , , , , and . DATE, page 20008-20013. IEEE Computer Society, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications., , , , , , and . ICASSP, page 3112-3115. IEEE, (2002)HiBRID-SoC: a multi-core architecture for image and video applications., , , , , , and . ICIP (3), page 101-104. (2003)A multi-core SoC design for advanced image and video compression., , , , , , and . ICASSP (5), page 665-668. IEEE, (2005)A multi DSP board for real time SAR processing using the HiPAR-DSP 16., , , , , and . IGARSS, page 2750-2752. IEEE, (2002)HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing., , , , , and . VLSI-SOC, page 155-160. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing., , , , , , , , and . VLSI Signal Processing, 41 (1): 9-20 (2005)HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications., , , , , , , , and . DATE, page 20008-20013. IEEE Computer Society, (2003)A Study of Channeled DRAM Memory Architectures., , and . ICCD, page 261-266. IEEE Computer Society, (2000)HIBRID-SOC: a multi-core architecture for image and video applications., , , , , , and . SIGARCH Computer Architecture News, 32 (3): 55-61 (2004)