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Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture

S. Choudhary, D. Schwarz, H. Funk, K. Sharma, S. Sharma, and J. Schulze. 2022 International Symposium on Semiconductor Manufacturing (ISSM), page 1-4. (December 2022)
DOI: 10.1109/ISSM55802.2022.10027013

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A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge-on-Si Using HZO Internal Voltage AmplificationS. Choudhary, D. Schwarz, H. Funk, D. Weißhaupt, R. Khosla, S. Sharma, and J. Schulze. IEEE transactions on electron devices, 69 (5): 2725-2731 (2022)Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa ArchitectureS. Choudhary, D. Schwarz, H. Funk, K. Sharma, S. Sharma, and J. Schulze. 2022 International Symposium on Semiconductor Manufacturing (ISSM), page 1-4. (December 2022)Automatic Hyperlinking of Engineering Drawing Documents.P. Banerjee, S. Choudhary, S. Das, H. Majumdar, R. Roy, and B. Chaudhuri. DAS, page 102-107. IEEE Computer Society, (2016)Impact of Charge Trapping On Epitaxial p-Ge-on-p-Si and HfO2 Based Al/HfO2/p-Ge-on-p-Si/Al Structures Using Kelvin Probe Force Microscopy and Constant Voltage StressS. Choudhary, D. Schwarz, H. Funk, R. Khosla, S. Sharma, and J. Schulze. IEEE Transactions on Nanotechnology, (2021)Impact of Charge Trapping On Epitaxial p-Ge-on-p-Si and HfO2 Based Al/HfO2/p-Ge-on-p-Si/Al Structures Using Kelvin Probe Force Microscopy and Constant Voltage StressS. Choudhary, D. Schwarz, H. Funk, R. Khosla, S. Sharma, and J. Schulze. IEEE transactions on nanotechnology, (2021)Novel process integration flow of germanium-on-silicon FinFETs for low-power technologiesS. Choudhary, M. Yogesh, D. Schwarz, H. Funk, S. Ghosh, S. Sharma, J. Schulze, and K. Gonsalves. 41 (5): 052203 (2023)

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Disambiguation of "Choudhary, Sumit"

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Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture

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Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture