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Disambiguation of "Gopalakrishnan, Kailash"

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Overview of candidate device technologies for storage-class memory.

, , , , , and . IBM Journal of Research and Development, 52 (4-5): 449-464 (2008)

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PACT: Parameterized Clipping Activation for Quantized Neural Networks., , , , , and . CoRR, (2018)Exploiting approximate computing for deep learning acceleration., , , , and . DATE, page 821-826. IEEE, (2018)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator., , , , , , , , , and 3 other author(s). IEEE Micro, 39 (5): 102-111 (2019)A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel., , , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2019)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)Nanoscale electronic synapses using phase change devices., , , , , , , , , and 5 other author(s). JETC, 9 (2): 12:1-12:20 (2013)AdaComp : Adaptive Residual Gradient Compression for Data-Parallel Distributed Training., , , , , and . AAAI, page 2827-2835. AAAI Press, (2018)Accelerator Design for Deep Learning Training: Extended Abstract: Invited., , , , , , , , and . DAC, page 57:1-57:2. ACM, (2017)Deep Learning with Limited Numerical Precision., , , and . ICML, volume 37 of JMLR Workshop and Conference Proceedings, page 1737-1746. JMLR.org, (2015)