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DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator.

S. Venkataramani, J. Choi, V. Srinivasan, W. Wang, J. Zhang, M. Schaal, M. Serrano, K. Ishizaki, H. Inoue, E. Ogawa, M. Ohara, L. Chang, and K. Gopalakrishnan. IEEE Micro, 39 (5): 102-111 (2019)

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Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Big Chips.A. Kahng, and V. Srinivasan. IEEE Micro, 31 (4): 3-5 (2011)Analyzing the Cost of a Cache Miss Using Pipeline Spectroscopy.T. Puzak, A. Hartstein, P. Emma, V. Srinivasan, and A. Nadas. J. Instruction-Level Parallelism, (2008)SAFER: Stuck-At-Fault Error Recovery for Memories.N. Seong, D. Woo, V. Srinivasan, J. Rivers, and H. Lee. MICRO, page 115-124. IEEE Computer Society, (2010)SPATL: Honey, I Shrunk the Coherence Directory.H. Zhao, A. Shriraman, S. Dwarkadas, and V. Srinivasan. PACT, page 33-44. IEEE Computer Society, (2011)DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator.S. Venkataramani, J. Choi, V. Srinivasan, W. Wang, J. Zhang, M. Schaal, M. Serrano, K. Ishizaki, H. Inoue, E. Ogawa and 3 other author(s). IEEE Micro, 39 (5): 102-111 (2019)Scalable high performance main memory system using phase-change memory technology.M. Qureshi, V. Srinivasan, and J. Rivers. ISCA, page 24-33. ACM, (2009)A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel.E. Ogawa, K. Ishizaki, H. Inoue, S. Venkataramani, J. Choi, W. Wang, V. Srinivasan, M. Ohara, and K. Gopalakrishnan. COOL CHIPS, page 1-3. IEEE, (2019)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)RECAP: A region-based cure for the common cold (cache).J. Zebchuk, H. Cain, X. Tong, V. Srinivasan, and A. Moshovos. HPCA, page 83-94. IEEE Computer Society, (2013)Evaluating the performance of active cache management schemes.E. Tam, J. Rivers, V. Srinivasan, G. Tyson, and E. Davidson. ICCD, page 368-375. (1998)

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Disambiguation of "Srinivasan, Vijayalakshmi"

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DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator.

Please choose a person to relate this publication to

Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Srinivasan, Vijayalakshmi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator.

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Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Disambiguation

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DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator.