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A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel.

E. Ogawa, K. Ishizaki, H. Inoue, S. Venkataramani, J. Choi, W. Wang, V. Srinivasan, M. Ohara, and K. Gopalakrishnan. COOL CHIPS, page 1-3. IEEE, (2019)

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Error resilient MRF message passing architecture for stereo matching.J. Choi, E. Kim, R. Rutenbar, and N. Shanbhag. SiPS, page 348-353. IEEE, (2013)An FPGA implementation of speech recognition with weighted finite state transducers.J. Choi, K. You, and W. Sung. ICASSP, page 1602-1605. IEEE, (2010)Transmission Power Control with the Guaranteed Communication Reliability in WSN.D. Kim, Z. Jin, J. Choi, B. Lee, and J. Cho. IJDSN, (2015)DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator.S. Venkataramani, J. Choi, V. Srinivasan, W. Wang, J. Zhang, M. Schaal, M. Serrano, K. Ishizaki, H. Inoue, E. Ogawa and 3 other author(s). IEEE Micro, 39 (5): 102-111 (2019)Supporting handover in an IEEE 802.11p-based wireless access system.J. Choi, and H. Lee. Vehicular Ad Hoc Networks, page 75-80. ACM, (2010)Hardware and Software Co-optimization for the Initialization Failure of the ReRAM-based Cross-bar Array.Y. Kim, S. Kim, C. Yeh, V. Narayanan, and J. Choi. ACM J. Emerg. Technol. Comput. Syst., 16 (4): 36:1-36:19 (2020)A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel.E. Ogawa, K. Ishizaki, H. Inoue, S. Venkataramani, J. Choi, W. Wang, V. Srinivasan, M. Ohara, and K. Gopalakrishnan. COOL CHIPS, page 1-3. IEEE, (2019)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)Flexible and Expandable Speech Recognition Hardware with Weighted Finite State Transducers.K. You, J. Choi, and W. Sung. Signal Processing Systems, 66 (3): 235-244 (2012)Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform.J. Choi, and R. Rutenbar. IEEE Trans. Circuits Syst. Video Techn., 26 (2): 385-398 (2016)

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel.

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