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Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV., , and . IEEE Trans. VLSI Syst., 21 (1): 1-13 (2013)Architectural support of multiple hypervisors over single platform for enhancing cloud computing security., , , , and . Conf. Computing Frontiers, page 75-84. ACM, (2012)COMPASS: a programmable data prefetcher using idle GPU shaders., and . ASPLOS, page 297-310. ACM, (2010)Reducing energy of virtual cache synonym lookup using bloom filters., , , , and . CASES, page 179-189. ACM, (2006)Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching., , , and . TACO, 7 (1): 3:1-3:35 (2010)Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)., , , , , , , , , and 13 other author(s). IEEE Trans. Computers, 64 (1): 112-125 (2015)SAFER: Stuck-At-Fault Error Recovery for Memories., , , , and . MICRO, page 115-124. IEEE Computer Society, (2010)Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11., , , , and . IEICE Transactions, 93-B (8): 2082-2087 (2010)POD: A 3D-Integrated Broad-Purpose Acceleration Layer., , , , and . IEEE Micro, 28 (4): 28-40 (2008)Acceleration of bulk memory operations in a heterogeneous multicore architecture., , , , , , , and . PACT, page 423-424. ACM, (2012)