%0 Journal Article %1 journals/tvlsi/WooSL13 %A Woo, Dong Hyuk %A Seong, Nak Hee %A Lee, Hsien-Hsin S. %D 2013 %J IEEE Trans. VLSI Syst. %K dblp %N 1 %P 1-13 %T Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi21.html#WooSL13 %V 21

@article{journals/tvlsi/WooSL13, added-at = {2013-01-03T00:00:00.000+0100}, author = {Woo, Dong Hyuk and Seong, Nak Hee and Lee, Hsien-Hsin S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23628cb40fcca546d91fdd71fe9f8bd12/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2011.2176761}, interhash = {6ed67989f5aa916f1b67a4b803e9f366}, intrahash = {3628cb40fcca546d91fdd71fe9f8bd12}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 1, pages = {1-13}, timestamp = {2016-02-02T02:12:02.000+0100}, title = {Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi21.html#WooSL13}, volume = 21, year = 2013 }