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Enhancing delay fault coverage through low-power segmented scan.

, , , , and . IET Computers & Digital Techniques, 1 (3): 220-229 (2007)

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BTI and leakage aware dynamic voltage scaling for reliable low power cache memories., , , and . IOLTS, page 194-199. IEEE, (2015)Selective state retention design using symbolic simulation., , , and . DATE, page 1644-1649. IEEE, (2009)A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities., , and . DATE, page 10960-10965. IEEE Computer Society, (2003)Sub-clock power-gating technique for minimising leakage power during active mode., , , and . DATE, page 106-111. IEEE, (2011)Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint., , and . ISQED, page 368-373. IEEE Computer Society, (2007)Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation., , , , and . Asian Test Symposium, page 389-394. IEEE Computer Society, (2011)Diagnosis of power switches with power-distribution-network consideration., , , and . ETS, page 1-6. IEEE, (2015)Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing., , and . ITC, page 64-73. IEEE Computer Society, (2002)Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation., , , , and . IEEE Trans. on Circuits and Systems, 60-I (11): 2953-2961 (2013)Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry., , , and . IEEE Trans. on Circuits and Systems, 56-II (4): 285-289 (2009)