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A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.

S. Lin, H. Yang, and R. Luo. ISCAS, page 1401-1404. IEEE, (2007)

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Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

Other publications of authors with the same name

Power Gating Aware Task Scheduling in MPSoC.Y. Wang, J. Xu, Y. Xu, W. Liu, and H. Yang. IEEE Trans. VLSI Syst., 19 (10): 1801-1812 (2011)A "Near-the-Best" System-Level Design Methodology of Multi-Core H.264 Video Decoder Based on the Parallelized Multi-Core Simulator.B. Xia, F. Qiao, Z. Du, D. Zhu, and H. Yang. Journal of Circuits, Systems, and Computers, (2012)On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.W. Liu, Y. Wang, X. Wang, J. Xu, and H. Yang. IEEE Trans. Parallel Distrib. Syst., 24 (4): 767-777 (2013)NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation.X. Chen, Y. Wang, and H. Yang. IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (2): 261-274 (2013)Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things.Y. Wang, Y. Liu, C. Wang, Z. Li, X. Sheng, H. Lee, N. Chang, and H. Yang. IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (2): 173-186 (2016)Modeling the Impact of Process Variation on Critical Charge Distribution.Q. Ding, R. Luo, H. Wang, H. Yang, and Y. Xie. SoCC, page 243-246. IEEE, (2006)FPGA and GPU implementation of large scale SpMV.Y. Shan, T. Wu, Y. Wang, B. Wang, Z. Wang, N. Xu, and H. Yang. SASP, page 64-70. IEEE Computer Society, (2010)Modeling of PMOS NBTI Effect Considering Temperature Variation.H. Luo, Y. Wang, K. He, R. Luo, H. Yang, and Y. Xie. ISQED, page 139-144. IEEE Computer Society, (2007)TSV-aware topology generation for 3D Clock Tree Synthesis.W. Liu, H. Du, Y. Wang, Y. Ma, Y. Xie, J. Quan, and H. Yang. ISQED, page 300-307. IEEE, (2013)A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design.B. Xia, F. Qiao, H. Yang, and H. Wang. ISQED, page 191-197. IEEE, (2010)

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Disambiguation of "Yang, Huazhong"

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A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.

Please choose a person to relate this publication to

Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Yang, Huazhong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.

Please choose a person to relate this publication to

Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.