%0 Journal Article %1 journals/tvlsi/WangXXLY11 %A Wang, Yu %A Xu, Jiang %A Xu, Yan %A Liu, Weichen %A Yang, Huazhong %D 2011 %J IEEE Trans. VLSI Syst. %K dblp %N 10 %P 1801-1812 %T Power Gating Aware Task Scheduling in MPSoC. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#WangXXLY11 %V 19

@article{journals/tvlsi/WangXXLY11, added-at = {2012-09-18T00:00:00.000+0200}, author = {Wang, Yu and Xu, Jiang and Xu, Yan and Liu, Weichen and Yang, Huazhong}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ff152a5a308f012ffd81d005adb058dd/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2010.2055907}, interhash = {cb2dde86f7f6d6c5d105b510d91fc354}, intrahash = {ff152a5a308f012ffd81d005adb058dd}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 10, pages = {1801-1812}, timestamp = {2016-02-02T02:11:55.000+0100}, title = {Power Gating Aware Task Scheduling in MPSoC.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#WangXXLY11}, volume = 19, year = 2011 }