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A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS., , , and . ESSCIRC, page 243-246. IEEE, (2014)Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS., , , , and . IEEE Trans. on Circuits and Systems, 63-I (6): 806-817 (2016)Joint replenishment policy with backordering and special sale., , and . Int. J. Systems Science, 46 (7): 1172-1198 (2015)Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS., and . A-SSCC, page 1-4. IEEE, (2015)A stochastic model of tumor angiogenesis., , and . Comp. in Bio. and Med., 38 (9): 1007-1011 (2008)A 65 nm single stage 28 fJ/cycle 0.12 to 1.2V level-shifter., and . ISCAS, page 990-993. IEEE, (2014)A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs., , , , , and . VLSI-SoC, page 380-385. IEEE, (2013)A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI., , , , , and . ESSCIRC, page 429-432. IEEE, (2016)PPF-Dependent Fixed Point Results for Multi-Valued ϕ-F-Contractions in Banach Spaces and Applications., , , , and . Symmetry, 11 (11): 1375 (2019)A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS., , , , , and . ESSCIRC, page 321-324. IEEE, (2012)