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Disambiguation of "Sherazi, S. M. Yasser"

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A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

, , , , , and . ESSCIRC, page 321-324. IEEE, (2012)

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M. S. Fischer

S. Schumann

S. Seemann

S. Wartzack

Boettinger S

 

Other publications of authors with the same name

Supply-voltage down conversion for digital CMOS designs., , , and . ICECS, page 339-342. IEEE, (2014)Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain., , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (4-5): 494-504 (2013)Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain., , , , and . ISCAS, page 837-840. IEEE, (2011)Low Power Analog and Digital (7, 5) Convolutional Decoders in 65 nm CMOS., , , , and . IEEE Trans. on Circuits and Systems, 62-I (7): 1863-1872 (2015)Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS., , and . NORCHIP, page 1-4. IEEE, (2011)Analog and digital approaches for an energy efficient low complexity channel decoder., , , , and . ISCAS, page 1564-1567. IEEE, (2013)Ultra low power transceivers for wireless sensors and body area networks., , , , , , , , , and 3 other author(s). ISMICT, page 1-5. IEEE, (2014)A Receiver Architecture for Devices in Wireless Body Area Networks., , , , , , , , , and 3 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (1): 82-95 (2012)Synthesis strategies for sub-VT systems., , , , and . ECCTD, page 552-555. IEEE, (2011)A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS., , , and . ICECS, page 448-451. IEEE, (2012)