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bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

P. Meinerzhagen, O. Andersson, B. Mohammadi, S. Sherazi, A. Burg, and J. Rodrigues. ESSCIRC, page 321-324. IEEE, (2012)

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Elke Peter University of Stuttgart

Benjamin Burger University of Stuttgart

Univ. -Prof. Dr. Rene Peters University of Stuttgart

Bernd Peters University of Stuttgart

Alexander Peter University of Stuttgart

Other publications of authors with the same name

An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity.H. Kroll, S. Zwicky, B. Weber, C. Roth, C. Benkeser, A. Burg, and Q. Huang. ESSCIRC, page 203-206. IEEE, (2014)Random sampling ADC for sparse spectrum sensing.P. Maechler, N. Felber, and A. Burg. EUSIPCO, page 1200-1204. IEEE, (2011)A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code.P. Giard, A. Balatsoukas-Stimming, T. Müller, A. Burg, C. Thibeault, and W. Gross. CoRR, (2017)A Fully-Unrolled LDPC Decoder Based on Quantized Message Passing.A. Balatsoukas-Stimming, M. Meidlinger, R. Ghanaatian, G. Matz, and A. Burg. CoRR, (2015)Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency.O. Afisiadis, A. Austin, A. Balatsoukas-Stimming, and A. Burg. CoRR, (2016)Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes.Y. Shen, A. Balatsoukas-Stimming, X. You, C. Zhang, and A. Burg. IEEE Wirel. Commun. Lett., 11 (2): 391-395 (2022)Synthesis strategies for sub-VT systems.P. Meinerzhagen, O. Andersson, S. Sherazi, A. Burg, and J. Rodrigues. ECCTD, page 552-555. IEEE, (2011)Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.I. Kazi, P. Meinerzhagen, P. Gaillardon, D. Sacchetto, Y. Leblebici, A. Burg, and G. Micheli. IEEE Trans. on Circuits and Systems, 61-I (11): 3155-3164 (2014)Statistical fault injection for impact-evaluation of timing errors on application performance.J. Constantin, A. Burg, Z. Wang, A. Chattopadhyay, and G. Karakonstantis. DAC, page 13:1-13:6. ACM, (2016)Approximate computing for unreliable silicon.A. Burg. DTIS, page 1. IEEE, (2016)

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Disambiguation of "Burg, Andreas Peter"

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A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

Please choose a person to relate this publication to

Elke Peter University of Stuttgart

Benjamin Burger University of Stuttgart

Univ. -Prof. Dr. Rene Peters University of Stuttgart

Bernd Peters University of Stuttgart

Alexander Peter University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Burg, Andreas Peter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

Please choose a person to relate this publication to

Elke Peter University of Stuttgart

Benjamin Burger University of Stuttgart

Univ. -Prof. Dr. Rene Peters University of Stuttgart

Bernd Peters University of Stuttgart

Alexander Peter University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.