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Voltage emergency prediction: Using signatures to reduce operating margins.

, , , , , and . HPCA, page 18-29. IEEE Computer Society, (2009)

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Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity., , , , , and . IEEE Micro, 30 (1): 110 (2010)Power management of multi-core chips: Challenges and pitfalls., , , , , , , , , and 1 other author(s). DATE, page 977-982. IEEE, (2012)Understanding voltage variations in chip multiprocessors using a distributed power-delivery network., , , , and . DATE, page 624-629. EDA Consortium, San Jose, CA, USA, (2007)Towards a software approach to mitigate voltage emergencies., , , , and . ISLPED, page 123-128. ACM, (2007)Resilient Architecture Design for Voltage Variation, and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2013)System level analysis of fast, per-core DVFS using on-chip switching regulators., , , and . HPCA, page 123-134. IEEE Computer Society, (2008)Error Tolerance in Server Class Processors., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (7): 945-959 (2011)Performance Implications of Periodic Checkpointing on Large-Scale Cluster Systems., , , and . IPDPS, IEEE Computer Society, (2005)Configurable Detection of SDC-causing Errors in Programs., , , , and . ACM Trans. Embedded Comput. Syst., 16 (3): 88:1-88:25 (2017)GPUVolt: modeling and characterizing voltage noise in GPU architectures., , , , and . ISLPED, page 141-146. ACM, (2014)