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Disambiguation of "Wei, Gu-Yeon"

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System level analysis of fast, per-core DVFS using on-chip switching regulators.

, , , and . HPCA, page 123-134. IEEE Computer Society, (2008)

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Wei Yu University of Stuttgart

Junyuan Gu University of Stuttgart

Dr. rer. nat. Ran Wei University of Stuttgart

Wei Zhang University of Stuttgart

Do Yeon Kim University of Stuttgart

 

Other publications of authors with the same name

Pipelined parallel architecture for high throughput MAP detectors., , and . ISCAS (2), page 505-508. IEEE, (2004)A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance., , , and . J. Solid-State Circuits, 43 (4): 855-863 (2008)An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery., , , and . J. Solid-State Circuits, 44 (11): 3120-3130 (2009)DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications., , , and . J. Solid-State Circuits, 53 (9): 2722-2731 (2018)Process Variation Tolerant 3T1D-Based Cache Architectures., , , and . MICRO, page 15-26. IEEE Computer Society, (2007)Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling., , , , , , and . MICRO, page 77-88. IEEE Computer Society, (2010)Network Pruning for Low-Rank Binary Indexing., , , , and . CoRR, (2019)Structured Compression by Unstructured Pruning for Sparse Quantized Neural Networks., , , , , and . CoRR, (2019)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis., , , , and . IEEE Trans. on Circuits and Systems, 65-II (10): 1440-1444 (2018)A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction., , and . CICC, page 459-462. IEEE, (2008)