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Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)Global Routing., and . Encyclopedia of Algorithms, (2016)Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (6): 905-917 (2013)Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (2): 185-196 (2010)Skew Management of NBTI Impacted Gated Clock Trees., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (6): 918-927 (2013)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)Chemical-mechanical polishing aware application-specific 3D NoC design., , , and . ICCAD, page 207-212. IEEE Computer Society, (2011)Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC., , , , and . ICCAD, page 563-570. IEEE Computer Society, (2011)