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An FPGA for Implementing Asynchronous Circuits., , , and . IEEE Design & Test of Computers, 11 (3): 60-69 (1994)Bounded Delay Timing Analysis of a Class of CSP Programs., and . Formal Methods in System Design, 11 (3): 265-294 (1997)Synthesis of asynchronous control circuits with automatically generated relative timing assumptions., , , and . ICCAD, page 324-331. IEEE Computer Society, (1999)Gate sizing and device technology selection algorithms for high-performance industrial designs., , and . ICCAD, page 724-731. IEEE Computer Society, (2011)Efficient Timing Analysis of a Class of Petri Nets., and . CAV, volume 939 of Lecture Notes in Computer Science, page 423-436. Springer, (1995)An improved benchmark suite for the ISPD-2013 discrete cell sizing contest., , , , , and . ISPD, page 168-170. ACM, (2013)ALIGN: Open-Source Analog Layout Automation from the Ground Up., , , , , , , , and . DAC, page 77. ACM, (2019)CAD Directions for High Performance Asynchronous Circuits., , , , , , and . DAC, page 116-121. ACM Press, (1999)Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries., and . DAC, page 83-88. ACM, (2011)Standard cell routing via boolean satisfiability., and . DAC, page 603-612. ACM, (2012)