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A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application., , , , , and . J. Solid-State Circuits, 46 (7): 1596-1605 (2011)A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation., , , , , , and . ISSCC, page 566-567. IEEE, (2008)A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 168-170. IEEE, (2012)A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS., , , , , and . ISSCC, page 70-72. IEEE, (2012)A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement., , , , , , and . J. Solid-State Circuits, 47 (7): 1646-1658 (2012)A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 47 (12): 3184-3196 (2012)A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique., , , , , , , and . J. Solid-State Circuits, 48 (7): 1721-1729 (2013)A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control., , , , , , and . ESSCIRC, page 131-134. IEEE, (2011)MIMO techniques for high data rate radio communications., , and . CICC, page 141-148. IEEE, (2008)A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS., , , , , , , , and . J. Solid-State Circuits, 51 (12): 2992-3004 (2016)