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A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating., , and . J. Solid-State Circuits, 50 (2): 464-475 (2015)A 4.68Gb/s belief propagation polar decoder with bit-splitting register file., , , and . VLSIC, page 1-2. IEEE, (2014)Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation., , and . FPGA, page 167-170. ACM, (2012)Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM., , , and . J. Solid-State Circuits, 49 (3): 783-794 (2014)A case for custom silicon in enabling low-cost information technology for developing regions., , , , , , , , , and 8 other author(s). ACM DEV, page 22. ACM, (2010)A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM., , , and . VLSIC, page 114-115. IEEE, (2012)A low-cost audio computer for information dissemination among illiterate people groups., , , , , , , , , and 8 other author(s). CICC, page 1-4. IEEE, (2012)A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating., , and . ISSCC, page 422-423. IEEE, (2013)High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders., , and . ISCAS, page 2625-2628. IEEE, (2012)