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A 4.68Gb/s belief propagation polar decoder with bit-splitting register file.

, , , and . VLSIC, page 1-2. IEEE, (2014)

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Minimum supply voltage for sequential logic circuits in a 22nm technology., , , , and . ISLPED, page 181-186. IEEE, (2013)1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks., , and . VLSIC, page 246-. IEEE, (2015)A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS., , and . J. Solid-State Circuits, 53 (10): 2818-2827 (2018)Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM., , , and . J. Solid-State Circuits, 49 (3): 783-794 (2014)Editorial., , , , , , , , , and 35 other author(s). IEEE Trans. VLSI Syst., 25 (1): 1-20 (2017)Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes., , , , and . IEEE Trans. Information Theory, 56 (1): 181-201 (2010)Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices., , , , and . IEEE Trans. Communications, 57 (11): 3258-3268 (2009)A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM., , , and . VLSIC, page 114-115. IEEE, (2012)Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes., , and . IEEE Trans. on Circuits and Systems, 66-I (10): 4032-4043 (2019)DNC-Aided SCL-Flip Decoding of Polar Codes., and . GLOBECOM, page 1-6. IEEE, (2021)