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1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks.

, , and . VLSIC, page 246-. IEEE, (2015)

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Vanessa Costalonga Martins University of Stuttgart

Towards Modular Natural Fiber-Reinforced Polymer Architecture, , , , and . Distributed Proximities : Proceedings of the 40th Annual Conference of the Association of Computer Aided Design in Architecture, Volume I : Technical papers, keynote conversations, page 564-573. Philadelphia, Association for Computer Aided Design in Architecture (ACADIA), (2020)

Anh Chu University of Stuttgart

A 263GHz 32-Channel EPR-on-a-Chip Injection-Locked VCO-Array, , , , and . 2023 IEEE International Solid-State Circuits Conference (ISSCC), page 20-22. IEEE, (2023)
 

Other publications of authors with the same name

Computational sprinting., , , , , , and . HPCA, page 249-260. IEEE Computer Society, (2012)Memory Assignment for Multiprocessor Caches through Grey Coloring., , , and . PARLE, volume 817 of Lecture Notes in Computer Science, page 351-362. Springer, (1994)Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming., , and . JSSPP, volume 1291 of Lecture Notes in Computer Science, page 277-298. Springer, (1997)A True Single-Phase 8-bit Adiabatic Multiplier., , and . DAC, page 758-763. ACM, (2001)Design of a high-throughput low-power IS95 Viterbi decoder., and . DAC, page 263-268. ACM, (2002)Parallelizing post-placement timing optimization., , and . IPDPS, IEEE, (2006)Retiming and clock scheduling for digital circuit optimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (2): 184-203 (2002)Utilizing Dark Silicon to Save Energy with Computational Sprinting., , , , , , and . IEEE Micro, 33 (5): 20-28 (2013)Designing for Responsiveness with Computational Sprinting., , , , , , and . IEEE Micro, 33 (3): 8-15 (2013)A 225 MHz resonant clocked ASIC chip., , , and . ISLPED, page 48-53. ACM, (2003)