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Estimating the Signal-to-Noise Ratio Under Repeated Sampling of the Same Centered Signal: Applications to Side-Channel Attacks on a Cryptoprocessor.

, and . IEEE Trans. Information Theory, 64 (9): 6333-6339 (2018)

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Voltage Spikes on the Substrate to Obtain Timing Faults., , , , and . DSD, page 483-486. IEEE Computer Society, (2013)Techniques for EM Fault Injection: Equipments and Experimental Results.. FDTC, page 3-4. IEEE Computer Society, (2012)A model of the leakage in the frequency domain and its application to CPA and DPA., , , , and . J. Cryptographic Engineering, 4 (3): 197-212 (2014)Security evaluation of dual rail logic against DPA attacks., , , and . VLSI-SoC, page 181-186. IEEE, (2006)Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier., , , , , , and . ISVLSI, page 316-321. IEEE Computer Society, (2008)Gate Sizing for Low Power Design., , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 301-312. Kluwer, (2001)Statistical timing characterization., , , and . ISSoC, page 1-4. IEEE, (2012)Circuit sizing method under delay constraint., , , and . ISCAS, IEEE, (2006)Logical effort model extension to propagation delay representation., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (9): 1677-1684 (2006)Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography., , , , and . VLSI-SoC, volume 360 of IFIP Advances in Information and Communication Technology, page 135-155. Springer, (2009)