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Disambiguation of "Miura, Noriyuki"

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47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking.

, , , , , , and . CICC, page 449-452. IEEE, (2009)

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Other publications of authors with the same name

A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 249-256 (2012)A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking., , and . ISSCC, page 440-441. IEEE, (2010)An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM., , , and . ISSCC, page 436-437. IEEE, (2010)A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking., , , , , , , and . ISSCC, page 244-245. IEEE, (2009)A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking., , , , and . ISSCC, page 490-492. IEEE, (2011)A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping., , , and . ISSCC, page 358-608. IEEE, (2007)Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link., , , , , , , and . IEICE Transactions, 90-C (4): 829-835 (2007)Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication., , , and . J. Solid-State Circuits, 47 (11): 2643-2653 (2012)A 30 Gb/s/Link 2.2 Tb/s/mm 2 Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface., , and . J. Solid-State Circuits, 46 (11): 2552-2559 (2011)A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards., , , , and . J. Solid-State Circuits, 47 (10): 2496-2504 (2012)