We report room temperature current voltage characteristics of Si p+-i-n+ Esaki diodes integrated on silicon substrates. The diodes were fabricated by low-temperature molecular beam epitaxy. Very high and abrupt p- and n-type dopant transitions into the 1020 cm−3 ranges are achieved by boron and antimony, respectively. The integrated devices are realized without a postgrowth annealing step. The silicon Esaki diodes show negative differential resistance at room temperature with excellent peak to valley current ratios up to 3.94. A variation in the thickness of the silicon tunneling barrier changes the peak current density over three orders of magnitude.
%0 Journal Article
%1 oehme2009esaki
%A Oehme, M
%A Hähnel, D
%A Werner, J
%A Kaschel, M
%A Kirfel, O
%A Kasper, E
%A Schulze, J
%B Applied Physics Letters
%D 2009
%I American Institute of Physics
%J Appl. Phys. Lett.
%K iht j.schulze.iht journal
%N 24
%P 242109--
%R 10.1063/1.3274136
%T Si Esaki diodes with high peak to valley current ratios
%U https://doi.org/10.1063/1.3274136
%V 95
%X We report room temperature current voltage characteristics of Si p+-i-n+ Esaki diodes integrated on silicon substrates. The diodes were fabricated by low-temperature molecular beam epitaxy. Very high and abrupt p- and n-type dopant transitions into the 1020 cm−3 ranges are achieved by boron and antimony, respectively. The integrated devices are realized without a postgrowth annealing step. The silicon Esaki diodes show negative differential resistance at room temperature with excellent peak to valley current ratios up to 3.94. A variation in the thickness of the silicon tunneling barrier changes the peak current density over three orders of magnitude.
@article{oehme2009esaki,
abstract = {We report room temperature current voltage characteristics of Si p+-i-n+ Esaki diodes integrated on silicon substrates. The diodes were fabricated by low-temperature molecular beam epitaxy. Very high and abrupt p- and n-type dopant transitions into the 1020 cm−3 ranges are achieved by boron and antimony, respectively. The integrated devices are realized without a postgrowth annealing step. The silicon Esaki diodes show negative differential resistance at room temperature with excellent peak to valley current ratios up to 3.94. A variation in the thickness of the silicon tunneling barrier changes the peak current density over three orders of magnitude.},
added-at = {2018-11-16T14:53:23.000+0100},
author = {Oehme, M and Hähnel, D and Werner, J and Kaschel, M and Kirfel, O and Kasper, E and Schulze, J},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/20a58cabeb86754d994d11ec2315003f2/ihtpublikation},
booktitle = {Applied Physics Letters},
comment = {doi: 10.1063/1.3274136},
doi = {10.1063/1.3274136},
interhash = {c7e4d4b114cfb239e634ae0fdae66011},
intrahash = {0a58cabeb86754d994d11ec2315003f2},
issn = {00036951},
journal = {Appl. Phys. Lett.},
keywords = {iht j.schulze.iht journal},
month = dec,
number = 24,
pages = {242109--},
publisher = {American Institute of Physics},
timestamp = {2018-11-16T13:53:23.000+0100},
title = {Si Esaki diodes with high peak to valley current ratios},
url = {https://doi.org/10.1063/1.3274136},
volume = 95,
year = 2009
}