%0 Conference Paper %1 conf/vlsid/LeeSS16 %A Lee, William %A Sharma, Tannu %A Stevens, Kenneth S. %B VLSI Design %D 2016 %I IEEE Computer Society %K dblp %P 511-516 %T Path Based Timing Validation for Timed Asynchronous Design. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#LeeSS16 %@ 978-1-4673-8700-2

@inproceedings{conf/vlsid/LeeSS16, added-at = {2016-03-21T00:00:00.000+0100}, author = {Lee, William and Sharma, Tannu and Stevens, Kenneth S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2263f402702a1aa6e57f289d0aa9d6beb/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2016}, ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2016.111}, interhash = {438f6b09bf30715b47190d27ae67000b}, intrahash = {263f402702a1aa6e57f289d0aa9d6beb}, isbn = {978-1-4673-8700-2}, keywords = {dblp}, pages = {511-516}, publisher = {IEEE Computer Society}, timestamp = {2016-03-22T10:34:40.000+0100}, title = {Path Based Timing Validation for Timed Asynchronous Design.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#LeeSS16}, year = 2016 }