%0 Journal Article %1 journals/tvlsi/TongZMLLZL17 %A Tong, Yufeng %A Zhang, Wei %A Ma, Yung-Cheng %A Liu, Yanyan %A Liang, Yu %A Zhang, Tai %A Luo, Haowen %D 2017 %J IEEE Trans. VLSI Syst. %K dblp %N 4 %P 1329-1341 %T Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP Processor. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#TongZMLLZL17 %V 25

@article{journals/tvlsi/TongZMLLZL17, added-at = {2019-12-02T00:00:00.000+0100}, author = {Tong, Yufeng and Zhang, Wei and Ma, Yung-Cheng and Liu, Yanyan and Liang, Yu and Zhang, Tai and Luo, Haowen}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/241326b5019ef5619444d773ffb1477de/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2016.2636419}, interhash = {01f9fec35184fcc7d8b8a2443affe506}, intrahash = {41326b5019ef5619444d773ffb1477de}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 4, pages = {1329-1341}, timestamp = {2019-12-11T12:49:32.000+0100}, title = {Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP Processor.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#TongZMLLZL17}, volume = 25, year = 2017 }