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Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation., , and . VLSI Design, page 369-374. IEEE Computer Society, (2010)A Top-Down Microsystems Design Methodology and Associated Challenges ., , , , , and . DATE, page 20292-20296. IEEE Computer Society, (2003)Top-down and bottom-up approaches to stable clock synthesis., , and . ICECS, page 575-578. IEEE, (2003)On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits., , , and . ISQED, page 815-820. IEEE Computer Society, (2008)Controlled-Load Limited Switch Dynamic Logic Circuit., , , , and . ISQED, page 83-87. IEEE Computer Society, (2005)Analysis and Optimization of Enhanced MTCMOS Scheme., , and . VLSI Design, page 234-239. IEEE Computer Society, (2004)A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference., , , , , , and . DAC, page 520-525. ACM, (2003)Optimization objectives and models of variation for statistical gate sizing., , , , and . ACM Great Lakes Symposium on VLSI, page 313-316. ACM, (2005)A dual-VDD boosted pulsed bus technique for low power and low leakage operation., , , , and . ISLPED, page 73-78. ACM, (2006)Approaches to run-time and standby mode leakage reduction in global buses., , , , , and . ISLPED, page 188-193. ACM, (2004)