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Disambiguation of "Brown, Richard B."

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Controlled-Load Limited Switch Dynamic Logic Circuit.

, , , , and . ISQED, page 83-87. IEEE Computer Society, (2005)

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Dr. phil. Niklas Brown University of Stuttgart

B. Schlecht

Richard Völker University of Stuttgart

Univ. -Prof. Dr. Richard Dipper University of Stuttgart

Richard Powers University of Stuttgart

 

Other publications of authors with the same name

Parametric Yield Analysis and Optimization in Leakage Dominated Technologies., , , and . IEEE Trans. VLSI Syst., 15 (6): 613-623 (2007)Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise., , , , and . IEEE Trans. VLSI Syst., 18 (1): 166-170 (2010)Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation., , and . VLSI Design, page 369-374. IEEE Computer Society, (2010)Study and simulation of CMOS LC oscillator phase noise and jitter., , and . ISCAS (1), page 665-668. IEEE, (2003)A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces., , , , , , , and . ISCAS, page 2837-2840. IEEE, (2008)Power-aware global signaling strategies., , , , , and . ISCAS (1), page 604-607. IEEE, (2005)Clock tree synthesis with data-path sensitivity matching., , and . ASP-DAC, page 498-503. IEEE, (2008)Reducing parasitic BJT effects in partially depleted SOI digital logic circuits., , and . Microelectronics Journal, 39 (2): 275-285 (2008)Top-down and bottom-up approaches to stable clock synthesis., , and . ICECS, page 575-578. IEEE, (2003)A Top-Down Microsystems Design Methodology and Associated Challenges ., , , , , and . DATE, page 20292-20296. IEEE Computer Society, (2003)