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Analysis and Optimization of Enhanced MTCMOS Scheme.

, , and . VLSI Design, page 234-239. IEEE Computer Society, (2004)

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Technology trends and implications on SoC design.. SoCC, page 386. IEEE, (2011)Analysis and Optimization of Enhanced MTCMOS Scheme., , and . VLSI Design, page 234-239. IEEE Computer Society, (2004)Techniques for multilayer channel routing., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 7 (6): 698-712 (1988)Chameleon: a new multi-layer channel router., , , , , , and . DAC, page 495-502. IEEE Computer Society Press, (1986)Design methodology for a 1.0 GHz microprocessor., , , , , , , , , and 5 other author(s). ICCD, page 17-23. (1998)Area-oriented synthesis for pass-transistor logic., , , and . ICCD, page 160-167. (1998)A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits., , , and . ICCAD, page 689-692. IEEE Computer Society / ACM, (2003)Efficient techniques for gate leakage estimation., , , and . ISLPED, page 100-103. ACM, (2003)A semi-custom voltage-island technique and its application to high-speed serial links., , , , and . ISLPED, page 60-65. ACM, (2003)C5M-a control-logic layout synthesis system for high-performance microprocessors., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 17 (1): 14-23 (1998)