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Disambiguation of "Rajendran, Bipin"

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Phase Change Memory.

, , , , , , , and . Proceedings of the IEEE, 98 (12): 2201-2227 (2010)

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Other publications of authors with the same name

Efficient scrub mechanisms for error-prone emerging memories., , , , , and . HPCA, page 15-26. IEEE Computer Society, (2012)Neuromorphic computing with multi-memristive synapses., , , , , , , , , and . CoRR, (2017)Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC., , , and . 3DIC, page 1-5. IEEE, (2013)Live Demonstration: Image Classification Using Bio-inspired Spiking Neural Networks., , and . ISCAS, page 1-. IEEE, (2018)Mixed-precision architecture based on computational memory for training deep neural networks., , , , , and . ISCAS, page 1-5. IEEE, (2018)Acceleration of Convolutional Networks Using Nanoscale Memristive Devices., , and . EANN, volume 893 of Communications in Computer and Information Science, page 240-251. Springer, (2018)Self-consistent power/performance/reliability analysis for copper interconnects., , , , and . SLIP, page 17-22. ACM, (2004)Low-Power Neuromorphic Hardware for Signal Processing Applications: A review of architectural and system-level design approaches., , , , and . IEEE Signal Process. Mag., 36 (6): 97-110 (2019)Learning Algorithms and Signal Processing for Brain-Inspired Computing [From the Guest Editors]., , , , , , and . IEEE Signal Process. Mag., 36 (6): 12-15 (2019)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)