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Mixed-precision architecture based on computational memory for training deep neural networks., , , , , and . ISCAS, page 1-5. IEEE, (2018)Neuromorphic computing with multi-memristive synapses., , , , , , , , , and . CoRR, (2017)An efficient synaptic architecture for artificial neural networks., , , , , , , , and . NVMTS, page 1-4. IEEE, (2017)Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues., , , and . IRPS, page 6. IEEE, (2015)Impact of conductance drift on multi-PCM synaptic architectures., , , , , , and . NVMTS, page 1-4. IEEE, (2018)Deep learning acceleration based on in-memory computing., , , , , , , , , and 7 other author(s). IBM Journal of Research and Development, 63 (6): 7:1-7:16 (2019)Fatiguing STDP: Learning from spike-timing codes in the presence of rate codes., , , , , and . IJCNN, page 1823-1830. IEEE, (2017)Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses., , , , , and . CoRR, (2019)Mixed-precision training of deep neural networks using computational memory., , , , , and . CoRR, (2017)Accurate deep neural network inference using computational phase-change memory., , , , , , , , and . CoRR, (2019)