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Disambiguation of "Leblebici, Yusuf"

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An efficient synaptic architecture for artificial neural networks.

, , , , , , , , and . NVMTS, page 1-4. IEEE, (2017)

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Other publications of authors with the same name

A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories., , , and . ASP-DAC, page 835-840. IEEE, (2009)Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors., and . ISCAS (3), page 685-688. IEEE, (2004)Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage., and . ISCAS, page 1871-1874. IEEE, (2007)Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants., , , , , , and . ISCAS, page 533-536. IEEE, (2009)Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity., , and . ISCAS (5), page 453-456. IEEE, (2003)Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders., , , , and . ISCAS, page 1772-1775. IEEE, (2011)Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL., and . IEEE Trans. on Circuits and Systems, 59-II (12): 903-907 (2012)ILLIADS: a fast timing and reliability simulator for digital MOS circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 12 (9): 1387-1402 (1993)A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS., , and . VLSIC, page 180-. IEEE, (2015)A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic., , and . VLSI Design, 2000 (2): 115-128 (2000)