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SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems., , , , , , , , , and 4 other author(s). IEEE Trans. Computers, 68 (5): 765-783 (2019)Bayesian network early reliability evaluation analysis for both permanent and transient faults., , , , , , , and . IOLTS, page 7-12. IEEE, (2015)Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs., , , , , , , , , and 2 other author(s). DSN Workshops, page 6-9. IEEE Computer Society, (2018)Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions., , , and . IEEE Comput. Archit. Lett., 17 (2): 109-112 (2018)Differential Fault Injection on Microarchitectural Simulators., , , , and . IISWC, page 172-182. IEEE Computer Society, (2015)Online error detection in multiprocessor chips: A test scheduling study., , , , and . IOLTS, page 169-172. IEEE, (2013)Harnessing voltage margins for energy efficiency in multicore CPUs., , , , , and . MICRO, page 503-516. ACM, (2017)Accelerated online error detection in many-core microprocessor architectures., , , and . VTS, page 1-6. IEEE Computer Society, (2014)Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview., , , , , , , , , and 1 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 1204-1214 (2015)